1. Field of Invention
The present invention relates to an analog PLL circuit performing feedback control so that a phase of an oscillating output of a voltage controlling oscillator coincides with one of a standard input signal. Especially, the present invention relates to a technique that allows a lock-in time of the analog PLL circuit to shorten.
2. Related Background Art
FIG. 8 is a block diagram of a conventional analog PLL circuit. The analog PLL circuit of FIG. 8 comprises a divider 1, a phase comparator 2, a charge pump 3, a low pass filter 4, a voltage controlling oscillator 5, and a divider 6.
The divider 1 divides a standard input signal fin into M (M is an integer more than or equal to 2). The divider 6 divides the output of the voltage controlling oscillator 5 into N (N is an integer more than or equal to 2). The phase comparator 2 outputs a signal corresponding to deviation of the frequency and the phase of each output of the dividers 1 and 6. More specifically, in case the rising time of the output of the divider 1 is slower than the rising time of the output of the divider 6, the phase comparator 2 supplies an UP signal corresponding to the phase difference to the charge pump 3. Reversely, in case the rising time of the output of the divider 6 is slower than the rising time of the output of the divider 1, the phase comparator 2 supplies the DOWN signal corresponding to the phase difference to the charge pump 3.
In case the UP signal is supplied from the phase comparator 2, the charge pump 3 sets the input level of the low pass filter 4 to high level by means of performing charge. Reversely, in case the DOWN signal is supplied from the phase comparator 2, the charge pump 3 sets the input level of the low pass filter 4 to low level by means of performing discharge.
The low pass filter 4 eliminates unnecessary high frequency component included to the signal output from the charge pump. The output of the low pass filter 4 is supplied to the voltage controlling oscillator 5. The voltage controlling oscillator 5 outputs a signal with frequency corresponding to the voltage outputted from the low pass filter 4. The output fout of the voltage controlling oscillator 5 is used as an ultimate output and is inputted to the phase comparator 2 after being inputted to the divider 6 and divided by the divider 6.
As above mentioned, because the conventional analog PLL circuit inputs the signal dividing the output of the voltage controlling oscillator 5 and the signal dividing the standard input signal fin to the phase comparator 2, and performs the feedback control so that the frequency and the phase of the signals coincide, respectively, it is possible to output the oscillating signal with the coherent frequency and phase from the voltage controlling oscillator 5.
However, the conventional analog PLL circuit has a problem in that the output of the low pass filter may be inconstant just after a reset period finishes. That is, because the conventional analog PLL circuit resets only the divider 1 and 6, the phase comparator 2 and the voltage controlling oscillator 5, and did not reset the low pass filter 4, the output of the low pass filter 4 may be inconstant. The time necessary to settle the output frequency and the phase of the voltage controlling oscillator 5 (the time is called "lockin time" as follows) may become long.
Further, the oscillation frequency of the voltage controlling oscillator 5 may change due to the power supply voltage, the surrounding temperature, the manufacturing process, and so on. For example, FIG. 4 is a diagram showing the frequency property of the voltage controlling oscillator 5. In FIG. 4, the horizontal axis is the input voltage, and the vertical axis is the output frequency. The frequency property of the voltage controlling oscillator 5 changes due to the power supply voltage, the surrounding temperature, manufacturing process and so on. Assumed that a curb line A in FIG. 4 is an imaginary curb line, due to various dispersion, the frequency property changes like a curb line B or a curb line C. Accordingly, for example, even if the voltage V1 shown in FIG. 4 is inputted to the voltage controlling oscillator 5, due to various dispersion, the output frequency changes in a range of from f0 through f2.